1. Field of the Invention
The present invention relates to a data input circuit of a synchronous memory device, and more particularly to a data input circuit of a synchronous memory device, in which a data strobe signal can be used for a latch in a state of ensuring a full swing in a ultra high speed synchronous memory device.
2. Description of the Prior Art
A Double Data Rate (DDR) 2 Synchronous Dynamic Random Access Memory (SDRAM), which is a high speed synchronous memory device, represents a volatile memory device for storing data in a cell including one transistor and one capacitor. A DDR2 SDRAM synchronizes with an external clock signal to perform an internal operation, and performs a data write/read operation in a 4-bit prefetch scheme.
Hereinafter, an operation in which the memory device synchronizes with an external clock signal to write data in a 4-bit prefetch scheme will be described with reference to FIGS. 1 and 2.
A data input buffer 100 is a circuit for converting data inputted through a data pin (DQ) to data of a CMOS level. A delay unit 110 is a circuit for delaying the data outputted from the data input buffer 100 for a predetermined time period. An input data latch unit 120 is a circuit for latching the data outputted from the delay unit 110, and latches 4-bit data in a 4-bit prefetch operation.
A WDQS buffer 150 is a circuit for converting a write strobe signal WDQS applied from a memory controller to a signal of a CMOS level. The write strobe signal WDQS represents a data strobe signal applied in a write operation. A delay unit 160 delays the write strobe signal WDQS outputted from the WDQS buffer 150 for a predetermined time period, and outputs both a rising strobe signal rdqs synchronized with the rising edge of the write strobe signal WDQS and a falling strobe signal fdqs synchronized with the falling edge of the write strobe signal WDQS.
The input data latch unit 120 synchronizes with the rising strobe signal rdqs and the falling strobe signal fdqsr, and sequentially latches the data.
The 4-bit data stored in the input data latch unit 120 are transferred to an input data detection amplifier 130 through internal lines align 00, align 01, align 10 and align 11. The input data detection amplifier 130 amplifies the 4-bit data respectively in response to a data input strobe signal Dinstrobe, and applies the amplified data to a write driver 140. The write driver 140 stores the amplified data in a memory cell.
FIG. 2 is a waveform illustrating an operation of the data input unit of the memory device in FIG. 1.
Referring to FIG. 2, an “Ext clk” represents an external clock signal applied to the memory device. A “WDQS” is the write strobe signal, which represents a signal applied after predetermined time “tDQSS” from the time point at which a write command is applied. The “tDQSS” corresponds to about 0.75 tCK˜1.25 tCK (tCK represents a period of the “Ext clk”) after the write command is applied. FIG. 2 shows 8-bit data continuously applied through one data pin. Specifically, a “tDS” represents setup time and a “tDH” represents hold time.
In the 4-bit prefetch operation, the 4-bit data, which have been respectively synchronized with the rising edges a and c and the falling edges b and d of the write strobe signal WDQS, are aligned to the falling edge d and applied to the input data detection amplifier 130. Likewise, next 4-bit data are synchronized and aligned in the same manner and then applied to the input data detection amplifier 130. The 4-bit data applied in parallel to the input data detection amplifier 130 are synchronized with the data input strobe signal Dinstrobe and then applied to the write driver 140.
However, increase in the operation speed of the memory device causes the following problems.
FIGS. 3a and 3b are diagrams illustrating transformation of a clock signal in a high frequency operation.
As an operation frequency increases, the waveform of the write strobe signal WDQS transferred to the input data latch unit 120 via the delay unit 160 is transformed into an abnormal waveform as illustrated in FIG. 3b instead of a normal waveform as illustrated in FIG. 3a. This is because a transmission line for connecting the delay unit 160 to the input data latch unit 120 has a heavy load. Specifically, when the load of the transmission line increases, an RC delay also increases. Therefore, the signal may be distorted.
If the write strobe signal WDQS having the abnormal waveform as illustrated in FIG. 3b is applied to the input data latch unit 120, a desired operation cannot be performed. That is, the input data cannot be exactly latched and be aligned at an exact time point. As a result, the input data cannot be normally written.